Recently, interest in solid state disks is greatly increasing. A solid state disk uses a flash memory, a Synchronous Dynamic Random Access Memory (SDRAM) and the like, instead of a hard disk drive. Accordingly, since a mechanical driving device such as a motor used for a hard disk drive is not required in the solid state disk, the solid state disk may be operated without almost generating heat and noise. In addition, the solid state disk may be robust to external shocks, and may achieve a high data transmission rate, compared to the hard disk drive.
The solid state disk includes a plurality of memory banks, and a controller needs to select at least one of the plurality of memory banks to perform a read operation or a write operation. A general solid state disk selects at least one of a plurality of memory banks using firmware including a wear leveling algorithm that enables the plurality of memory banks to be almost evenly worn. However, when at least one memory bank is selected using the firmware, an operation of a Central Processing Unit (CPU) may be required, thereby causing various problems, such as a time delay.
Additionally, a plurality of memory banks are connected to a plurality of channels. For example, a four-channel solid state disk includes four channels, and a plurality of memory banks are connected to each of the four channels. Here, selecting a memory bank based on only states of memory banks, instead of based on a state of a channel connected to the selected memory bank may create a problem. In other words, when the channel connected to the selected memory bank is in a busy state, there is a need to wait until the channel enters an idle state to perform a read operation or a write operation with respect to the selected memory bank. Such waiting may cause a reduction in an overall performance of a solid state disk.